Analog-to-digital converter

ABSTRACT

An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuity. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.

CROSS-REFERENCE TO RELATED APPLICATIONS

This continuation application claims priority to U.S. patent applicationSer. No. 15/874,100, filed Jan. 18, 2018, which application isincorporated herein by reference in its entirety.

BACKGROUND

An analog-to-digital converter is an electronic circuit that converts ananalog signal into a digital value that represents the analog signal.One well-known type of analog-to-digital converter is a successiveapproximation register analog-to-digital converter. A successiveapproximation register analog-to-digital converter includes adigital-to-analog converter, which may be implemented with a series ofcapacitors and a number of switches. The capacitors have top plates thatare connected together, and bottom plates that are individuallyconnectable by way of the switches to an input voltage, a referencevoltage, and ground.

SUMMARY

A successive approximation register analog-to-digital converter thatincludes circuitry to compare a digital threshold value to an analoginput signal is disclosed herein. In one example, an analog-to-digitalconverter includes an input terminal, a digital-to-analog converter, acomparator, and successive approximation circuitry. The input terminalis configured to receive a multi-bit digital threshold value fromcircuitry external to the analog-to-digital converter. The successiveapproximation circuitry is coupled to the comparator and thedigital-to-analog converter. The successive approximation circuitry isconfigured to operate in a comparison mode and a conversion mode, and toprovide the multi-bit digital threshold value to the digital-to-analogconverter while operating in the comparison mode. The comparator iscoupled to the digital-to-analog converter and the successiveapproximation circuity. The comparator is configured to output a signalthat indicates whether an analog input signal exceeds an analogthreshold signal corresponding to the multi-bit digital threshold value.

In another example, a measurement system includes an analog multiplexerand a successive approximation register analog-to-digital convertercoupled to an output of the analog multiplexer. The analog-to-digitalconverter is configured to operate in a comparison mode and a conversionmode. In the comparison mode, the analog-to-digital converter isconfigured to convert a multi-bit digital threshold value received fromcircuitry external to the successive approximation registeranalog-to-digital converter to an analog threshold signal, and tocompare a signal received from the analog multiplexer to the analogthreshold signal.

In a further example, a successive approximation registeranalog-to-digital converter includes a first input terminal, a secondinput terminal, a capacitive digital-to-analog converter, a comparator,an output terminal, and successive approximation circuitry. The firstinput terminal is configured to receive a multi-bit digital thresholdvalue from circuitry external to the analog-to-digital converter. Thesecond input terminal configured to receive an analog input signal fromthe circuitry external to the analog-to-digital converter. Thecomparator is coupled to the capacitive digital-to-analog converter. Theoutput terminal is configured to provide an output of the comparator tothe circuitry external to the successive approximation registeranalog-to-digital converter. The successive approximation circuitry iscoupled to the comparator and the capacitive digital-to-analogconverter. The successive approximation circuitry is configured tooperate in a comparison mode and a conversion mode, and to provide, inthe comparison mode, the multi-bit digital threshold value to thecapacitive digital-to-analog converter. The capacitive digital-to-analogconverter is configured to convert the multi-bit digital threshold valueto an analog threshold signal, and to output a difference of the analogthreshold signal and the analog input signal. The comparator isconfigured to compare the difference to a reference voltage, and toprovide a result of the comparison at the output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of various examples, reference will now bemade to the accompanying drawings in which:

FIG. 1 shows a block diagram for a successive approximation registerdigital-to-analog converter that includes a conversion mode and acomparison mode in accordance with various examples;

FIG. 2 shows a schematic diagram for a capacitive digital-to-analogconverter suitable for use in a successive approximation registerdigital-to-analog converter in accordance with various examples;

FIG. 3 shows a block diagram for successive approximation circuitry thatincludes a conversion mode and a comparison mode in accordance withvarious examples;

FIG. 4 shows a block diagram for a measurement system that includes asuccessive approximation register digital-to-analog converter thatprovides a conversion mode and a comparison mode in accordance withvarious examples;

FIGS. 5 and 6 show timing diagrams for operation of a successiveapproximation register digital-to-analog converter in conversion andcomparison modes in accordance with various examples; and

FIG. 7 shows a flow diagram for a method for operating a successiveapproximation register digital-to-analog converter in conversion andcomparison mode in accordance with various examples;

FIG. 8 shows a block diagram for a successive approximation registerdigital-to-analog converter that includes a conversion mode and acomparison mode in accordance with various examples.

DETAILED DESCRIPTION

Certain terms have been used throughout this description and claims torefer to particular system components. As one skilled in the art willappreciate, different parties may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In this disclosure and claims, theterms “including” and “comprising” are used in an open-ended fashion,and thus should be interpreted to mean “including, but not limited to .. . .” Also, the term “couple” or “couples” is intended to mean eitheran indirect or direct wired or wireless connection. Thus, if a firstdevice couples to a second device, that connection may be through adirect connection or through an indirect connection via other devicesand connections. The recitation “based on” is intended to mean “based atleast in part on.” Therefore, if X is based on Y, X may be a function ofY and any number of other factors.

Various electronic systems include monitoring circuitry to determinewhether a signal is above or below a threshold. The threshold isprogrammable in some systems. In such systems, threshold accuracy andcomparison latency are important considerations, while numerical valuesof the monitored signal are not necessarily required. Some such systemsemploy analog comparators to determine whether a signal is above orbelow a threshold, and set the threshold using a resistive voltagedivider. Such systems are subject to a number of issues. For example,continuous current flow in the resistive voltage dividers leads toincreased power consumption, resistor tolerances result in inaccuracy ofthe threshold, and/or the threshold may not be easily changeable. Someof these issues are avoided by using a digital-to-analog converterrather than a resistive voltage divider. However, addition of componentsand the attendant cost is undesirable.

Some systems implement comparison to a threshold in the digital domain.In such systems an analog-to-digital converter periodically samples asignal and the digital output of the analog-to-digital converter iscompared to a digital threshold value. Successive approximation registeranalog-to-digital converters are often used for monitoring in thedigital domain. Latency in these systems is constrained by theconversion time of the analog-to-digital converter which may berelatively high (e.g., N clock cycles to produce an N-bit digitalvalue).

The present disclosure includes a successive approximation registeranalog-to-digital converter that operates in a conversion mode and acomparison mode. In the conversion mode, the successive approximationregister analog-to-digital converter executes a binary search to convertan analog signal to a digital value. In the comparison mode, thesuccessive approximation register analog-to-digital converter comparesan analog input signal to an analog threshold signal generated in thesuccessive approximation register analog-to-digital converter from adigital threshold value received from a source external to thesuccessive approximation register analog-to-digital converter. Thecomparison mode is implemented using the digital-to-analog converter ofthe successive approximation register analog-to-digital converter togenerate the analog threshold signal. Accordingly, no additionaldigital-to-analog converter is needed. The voltage of the analogthreshold signal is easily changed by providing a different digitalthreshold value to the successive approximation registeranalog-to-digital converter. The successive approximation registeranalog-to-digital converter disclosed herein reduces latency ofmonitoring by providing a result of comparison in a single clock cycle,rather than the N clock cycles required to digitize the analog inputsignal for digital comparison.

FIG. 1 shows a block diagram for a successive approximation registeranalog-to-digital converter 100 that includes a conversion mode and acomparison mode in accordance with various examples. In the conversionmode, the successive approximation register analog-to-digital converter100 executes a binary search to convert the analog input signal 116 to adigital value. In the comparison mode, the successive approximationregister analog-to-digital converter 100 compares the analog inputsignal 116 to an analog threshold signal generated in the successiveapproximation register analog-to-digital converter 100 from a digitalthreshold value 108 (e.g., a multi-bit digital threshold value) receivedfrom a source external to the successive approximation registeranalog-to-digital converter 100.

The successive approximation register analog-to-digital converter 100includes successive approximation circuitry 102, a capacitivedigital-to-analog converter 104, a comparator 106, an input terminal120, an input terminal 122, an output terminal 118, and a mode selectterminal 126. The input terminal 120 is for receipt of the analog inputsignal 116. The input terminal 122 is for receipt of a digital thresholdvalue. The output terminal 118 is for providing a comparison result toan external circuit. The mode select terminal 126 is for receipt of amode select signal 124 that sets the successive approximation registeranalog-to-digital converter 100 to operate in conversion mode orcomparison mode. In various implementations, the input terminal 122 isprovided as a serial data input or a parallel data input for receipt ofthe digital threshold value.

The analog signal output 112 of the capacitive digital-to-analogconverter 104 is coupled to an input of the comparator 106. Thecomparator 106 also receives a reference voltage (e.g., ground) andcompares the analog signal output 112 to the reference voltage. Theresult of comparison of the analog signal output 112 and the referencevoltage (i.e., the comparison result 114) is provided to the outputterminal 118 and to the successive approximation circuitry 102. Inconversion mode, the successive approximation circuitry 102 applies thecomparison result 114 in a binary search to determine whether a last setbit of a digital value representing the analog input signal 116 shouldremain set or be reset. In the conversion mode, the successiveapproximation circuitry 102 disregards the digital threshold value 108.In the comparison mode, feedback from the comparator 106 is not appliedin the successive approximation circuitry 102, and the successiveapproximation circuitry 102 disregards the comparison result 114.

The capacitive digital-to-analog converter 104 generates the analogsignal output 112 based on control signals 110 provided by thesuccessive approximation circuitry 102. The capacitive digital-to-analogconverter 104 includes a plurality of capacitors and a plurality ofswitches. The control signals 110 set the switches as needed to producea desired analog signal output 112. FIG. 2 shows a schematic diagram foran implementation of the capacitive digital-to-analog converter 104suitable for use in the successive approximation registeranalog-to-digital converter 100. The capacitive digital-to-analogconverter 104 includes a plurality of capacitors 202, where onecapacitor 202 corresponds to each bit of the capacitivedigital-to-analog converter 104. While, the capacitive digital-to-analogconverter 104 is illustrated in FIG. 2 as an 8-bit digital-to-analogconverter, various implementations of the capacitive digital-to-analogconverter 104 include a different number of bits and a correspondingnumber of capacitors 202.

In the capacitive digital-to-analog converter 104, the capacitor 202Ahas capacitance C and corresponds to the least significant bit of thedigital-to-analog converter. Each successive capacitor 202 of thecapacitive digital-to-analog converter 104 has double the capacitance ofthe capacitor corresponding to the next lower bit. Accordingly,capacitor 202B has capacitance 2C, capacitor 202C has capacitance 4C,capacitor 202D has capacitance 64C, and capacitor 202E has capacitance128C. The capacitors 202 are coupled to switches 204 that switchablyconnect the lower plates of the capacitors 202 to Analog In, Vref,ground, or another voltage. The switch 206 switchably connects the topplate of the capacitors 202 to ground.

In the conversion mode, the control signals 110 generated by thesuccessive approximation circuitry 102 connect the capacitors 202 toAnalog In to capture a sample of Analog In, and thereafter in Nconversion cycles the control signals 110 successively switch eachcapacitor 202 to Vref and/or ground (via the switches 204) to performthe binary search for the N bit digital value that best represents thesample of Analog In.

In the comparison mode, the control signals 110 generated by thesuccessive approximation circuitry 102 connect the capacitors 202 toAnalog In to capture a sample of Analog In, and thereafter set theswitches 204 in accordance with the digital threshold value 108 receivedby the successive approximation circuitry 102. For example, for eachlogic “one” of the digital threshold value 108 corresponding switches204 are set to connect the capacitor 202 to Vref, and for each logic“zero” of the digital threshold value 108 corresponding switches 204 areset to connect the capacitor 202 to ground. Thus, in comparison mode,the successive approximation circuitry 102 generates the control signals110 to cause the capacitive digital-to-analog converter 104 to convertthe digital threshold value 108 to an analog threshold signal that iscombined with the sampled analog input signal 116 to produce an outputthat is a difference of the sampled analog input signal 116 and theanalog threshold signal.

FIG. 3 shows a block diagram for an implementation of the successiveapproximation circuitry 102 that provides a conversion mode and acomparison mode in accordance with various examples. The successiveapproximation circuitry 102 includes switch control circuitry 302, amultiplexer 304, conversion control circuitry 306, and comparisoncontrol circuitry 308. The conversion control circuitry 306 includescircuitry that operates in the conversion mode to control execution ofthe binary search for a digital output value 128 that best representsthe analog input signal 116. For example, various implementations of theconversion control circuitry 306 include state machine circuitry thatsequences through bit selection based on the comparison result 114, anda successive approximation register to store the digital value generatedduring the binary search.

In the comparison mode, implementations of the conversion controlcircuitry 306 disregard the comparison result 114 as no binary search isperformed and portions of the conversion control circuitry 306 are idleto reduce power consumption. The comparison control circuitry 308controls the operation of the capacitive digital-to-analog converter 104in comparison mode. The comparison control circuitry 308 includescircuitry that operates in the comparison mode to control operation ofthe capacitive digital-to-analog converter 104 for comparing the analoginput signal 116 (e.g., a sample of the analog input signal 116) to ananalog threshold signal corresponding to the digital threshold value108. For example, various implementations of the comparison controlcircuitry 308 include state machine circuitry that sets the switches 204to sample the analog input signal 116, and thereafter sets the switches204 to drive the digital threshold value 108 onto the capacitors 202. Insome implementations, the conversion control circuitry 306 andcomparison control circuitry 308 may be implemented as a single controlcircuit, such as a single state machine.

The multiplexer 304 selects either the digital value output by thecomparison control circuitry 308, including the digital threshold value108, or the digital value output by the conversion control circuitry 306to forward to the switch control circuitry 302. Selection is based onwhether the mode select signal 124 indicates operation in conversionmode or operation in comparison mode. For example, in someimplementations, the mode select signal 124 is set to a logic “one” toselect operation in comparison mode and the mode select signal 124 isset to a logic “zero” to select operation in conversion mode. Thedigital value 310 output by the multiplexer 304 is provided to theswitch control circuitry 302.

The switch control circuitry 302 generates the control signals 110 tocontrol the switches 204 of the capacitive digital-to-analog converter104 based on the digital value 310 received from the multiplexer 304.For example, each field of the digital value 310 causes the switchcontrol circuitry 302 to generate control signals 110 that set theswitches 204 connected to a capacitor 202 to connect the capacitor 202to Vref, ground, or the analog input signal 116.

FIG. 4 shows a block diagram for a measurement system 400 that includesa successive approximation register analog-to-digital converter 100 thatprovides a conversion mode and a comparison mode in accordance withvarious examples. The measurement system 400 includes sensors 402, ananalog multiplexer 404, the successive approximation registeranalog-to-digital converter 100, and a controller 406. In someimplementations, the controller 406 is a microcontroller, amicroprocessor, a digital signal processor, or other instructionexecution machine.

The sensors 402 are transducers that measure one or more parameters ofan operational environment. For example, the sensors 402 may includetemperature sensors, pressure sensors, speed sensors, voltage sensors,current sensors, or any other type of sensor. The sensors 402 arecoupled to the analog multiplexer 404, and outputs of the sensors 402are provided to the analog multiplexer 404.

The analog multiplexer 404 is coupled to the successive approximationregister analog-to-digital converter 100. The analog multiplexer 404selects an output of one of the sensors 402 to provide to the successiveapproximation register analog-to-digital converter 100 based on theselect signal 408 received from the controller 406. The controller 406sets the select signal 408 to route each output of the sensors 402 tothe successive approximation register analog-to-digital converter 100 asneeded from monitoring of the outputs of the sensors 402.

The controller 406 sets the digital threshold value 108 and the modeselect signal 124 as needed to monitor and/or digitize each output ofthe sensors 402. For example, the controller 406 sets the mode selectsignal 124 to configure the successive approximation registeranalog-to-digital converter 100 for operation in the comparison mode,sets the digital threshold value 108 to a value appropriate formonitoring the output of a given one of the sensors 402, and tests thecomparison result 114 generated by the successive approximation registeranalog-to-digital converter 100 to determine whether the output of agiven one of the sensors 402 is greater than or less than the digitalthreshold value 108. For example, output of a first sensor being greaterthan a first digital threshold value may trigger a first operation inthe controller 406, output of a second sensor being less than a seconddigital threshold value may trigger a second operation in the controller406. The successive approximation register analog-to-digital converter100 provides the comparison result 114 to the controller 406. In oneexample, if the comparison result 114 indicates that the output of agiven one of the sensors 402 exceeds the digital threshold value 108,then the controller 406 sets the mode select signal 124 to configure thesuccessive approximation register analog-to-digital converter 100 foroperation in the conversion mode to cause the successive approximationregister analog-to-digital converter 100 to digitize the output of agiven one of the sensors 402. The controller 406 receives the digitaloutput value 128 generated by the successive approximation registeranalog-to-digital converter 100, and applies further processing to thedigital output value 128, or provides the digital output value 128 toother circuitry or systems. If the comparison result 114 indicates thatthe output of a given one of the sensors 402 does not exceed the digitalthreshold value 108, then the controller 406 sets the digital thresholdvalue 108 to a value appropriate for monitoring a different input of theanalog multiplexer 404 (e.g., the output of a different one of thesensors 402), and sets the select signal 408 to route the signal presenton the different input of the analog multiplexer 404 to the successiveapproximation register analog-to-digital converter 100.

In some systems, the measurement system 400 is included in a controlsystem wherein the controller 406 or circuitry coupled to the controller406 applies the monitoring and measurements generated by the successiveapproximation register analog-to-digital converter 100 to adjust theoperation of systems coupled to the controller 406.

FIGS. 5 and 6 show timing diagrams for operation of a successiveapproximation register analog-to-digital converter in conversion andcomparison modes in accordance with various examples. FIG. 5 showstiming of the successive approximation register analog-to-digitalconverter 100 when operating in the conversion mode. In the conversionmode, the successive approximation register analog-to-digital converter100 produces a N-bit digital output value 128 in N conversion clockcycles plus the time required to sample the analog input signal 116 inthe capacitive digital-to-analog converter 104.

FIG. 6 shows timing of the successive approximation registeranalog-to-digital converter 100 when operating in the comparison mode.In the comparison mode, the successive approximation registeranalog-to-digital converter 100 produces a comparison result 114 in asingle conversion clock cycle. Thus, the successive approximationregister analog-to-digital converter 100 provides substantially fastercomparison of the analog input signal 116 to a threshold value thansystems that implement comparison in the digital domain without thecircuit overhead of additional comparators or DACs.

FIG. 7 shows a flow diagram for a method for operating a successiveapproximation register analog-to-digital converter 100 in conversion andcomparison modes in accordance with various examples. Though depictedsequentially as a matter of convenience, at least some of the actionsshown can be performed in a different order and/or performed inparallel. Additionally, some embodiments may perform only some of theactions shown.

In block 702, the successive approximation register analog-to-digitalconverter 100 is configured for operation in comparison mode. Forexample, in some implementations, the controller 400 sets the modeselect signal 124 to indicate that the successive approximation registeranalog-to-digital converter 100 is to operate in comparison mode. Inresponse to the mode select signal 124, the successive approximationcircuitry 102 is configured to set the capacitive digital-to-analogconverter 104 to produce an analog signal output 112 corresponding tothe digital threshold value 108.

In block 704, a sensor is selected for monitoring. For example, thecontroller 400 sets the select signal 408 to select a given one of thesensors 402 to be monitored by the successive approximation registeranalog-to-digital converter 100. In response to the select signal 408,the analog multiplexer 404 routes the output of the given one of thesensors 402 to the successive approximation register analog-to-digitalconverter 100.

In block 705, the successive approximation register analog-to-digitalconverter 100 (e.g., the capacitive digital-to-analog converter 104)acquires a sample of the analog input signal 116. For example, thecomparison control circuitry 308 sets the switches 204 to connect thecapacitors 202 to the analog input signal 116.

In block 706, a digital threshold value 108 is provided to thesuccessive approximation register analog-to-digital converter 100. Forexample, the controller 400 sets the digital threshold value 108 to avalue appropriate for monitoring the output of the sensors 402 selectedin block 704.

In block 708, the successive approximation register analog-to-digitalconverter 100 (i.e., the comparator 106 of the successive approximationregister analog-to-digital converter 100) is comparing the analog inputsignal 116 to the analog threshold signal corresponding to the digitalthreshold value 108. The analog threshold signal is a voltagecorresponding to the digital threshold value 108 provided in block 706.That is, the difference of the sampled analog input signal 116 and theanalog threshold signal is generated in the capacitive digital-to-analogconverter 104, and the output of the capacitive digital-to-analogconverter 104 is compared to a reference voltage by the comparator 106.If the comparison result 114 of the successive approximation registeranalog-to-digital converter 100 indicates that the analog input signal116 does not exceed the digital threshold value 108, then monitoring maycontinue with selection of a next sensor to monitor in block 704.

If, in block 708, the comparison result 114 of the successiveapproximation register analog-to-digital converter 100 indicates thatthe analog input signal 116 exceeds the digital threshold value 108,then, in block 710, the successive approximation registeranalog-to-digital converter 100 is configured for operation inconversion mode in some implementations. For example the controller 400sets the mode select signal 124 to indicate that the successiveapproximation register analog-to-digital converter 100 is to operate inconversion mode. In response to the mode select signal 124, thesuccessive approximation circuitry 102 performs a binary search todigitize the analog input signal 116.

In block 712, the digital output value 128 is the digitized output ofthe sensor selected in block 704. The controller 406 retrieves thedigital output value 128 and perform further processing, provide thedigital output value 128 to another system, etc.

FIG. 8 shows a block diagram for a successive approximation registeranalog-to-digital converter 800 that includes a conversion mode and acomparison mode in accordance with various examples. The 800 is similarto the 100, but includes a resistive digital-to-analog converter 804rather than the capacitive digital-to-analog converter 104. In theconversion mode, the successive approximation register analog-to-digitalconverter 800 executes a binary search to convert the analog inputsignal 816 to a digital value 828. In the comparison mode, thesuccessive approximation register analog-to-digital converter 800compares the analog input signal 816 to an analog threshold signalgenerated in the successive approximation register analog-to-digitalconverter 800 from a digital threshold value 808 (e.g., a multi-bitdigital threshold value) received from a source external to thesuccessive approximation register analog-to-digital converter 800.

The successive approximation register analog-to-digital converter 800includes successive approximation circuitry 802, a resistivedigital-to-analog converter 804, a comparator 806, an input terminal820, an input terminal 822, an output terminal 818, and a mode selectterminal 826. The input terminal 820 is for receipt of the analog inputsignal 816. The input terminal 822 is for receipt of a digital thresholdvalue. The output terminal 818 is for providing a comparison result toan external circuit. The mode select terminal 826 is for receipt of amode select signal 824 that sets the successive approximation registeranalog-to-digital converter 800 to operate in conversion mode orcomparison mode. In various implementations, the input terminal 822 isprovided as a serial data input or a parallel data input for receipt ofthe digital threshold value.

The analog signal output 812 of the resistive digital-to-analogconverter 804 is coupled to an input of the comparator 806. Thecomparator 806 is similar to the comparator 106. The comparator 806receives the analog input signal 816 via the input terminal 820 andcompares the analog signal output 812 to the analog input signal 816 (ora sample thereof). The result of comparison of the analog signal output812 and the analog input signal 816 (i.e., the comparison result 814) isprovided to the output terminal 818 and to the successive approximationcircuitry 802. The successive approximation circuitry 802 is similar tothe successive approximation circuitry 102, but includes circuitry toperform conversion and comparison using the resistive digital-to-analogconverter 804 rather than the capacitive digital-to-analog converter104. In conversion mode, the successive approximation circuitry 802applies the comparison result 814 in a binary search to determinewhether a last set bit of a digital value representing the analog inputsignal 816 should remain set or be reset. In the comparison mode,feedback from the comparator 806 is not applied in the successiveapproximation circuitry 802, and the successive approximation circuitry802 disregards the comparison result 814.

The resistive digital-to-analog converter 804 generates the analogsignal output 812 based on control signals 810 provided by thesuccessive approximation circuitry 802. The resistive digital-to-analogconverter 804 includes a plurality of resistors connected to produce anoutput voltage in response to the control signals 810. For example, someimplementations of the resistive digital-to-analog converter 804 includea resistor ladder that produces an output voltage in proportion to adigital value provided by the control signals 810. Some implementationsof the resistive digital-to-analog converter 804 include a tappedvoltage divider that produces an output voltage corresponding to adigital value provided by the control signals 810.

In the conversion mode, in N conversion cycles the control signals 810generated by the successive approximation circuitry 802 successivelyswitch the resistors of the resistive digital-to-analog converter 804 toperform the binary search for the N bit digital value that bestrepresents a sample of the analog input signal 816. In the comparisonmode, the control signals 810 generated by the successive approximationcircuitry 802 set the resistors of the resistive digital-to-analogconverter 804 to produce an analog signal output 812 that corresponds tothe digital threshold value 808 received by the successive approximationcircuitry 802. Thus, in comparison mode, the successive approximationcircuitry 802 generates the control signals 810 to cause the resistivedigital-to-analog converter 804 to convert the digital threshold value808 to an analog threshold signal that is compared to the analog inputsignal 116 by the comparator 806.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. An analog-to-digital converter, comprising: aninput terminal configured to receive a multi-bit digital threshold valuefrom circuitry external to the analog-to-digital converter; adigital-to-analog converter; successive approximation circuitry coupledto the digital-to-analog converter, the successive approximationcircuitry configured to: operate in a comparison mode and a conversionmode; and provide the multi-bit digital threshold value to thedigital-to-analog converter while operating in the comparison mode; anda comparator coupled to the digital-to-analog converter and thesuccessive approximation circuity, the comparator configured to output asignal that indicates whether an analog input signal exceeds an analogthreshold signal corresponding to the multi-bit digital threshold value.2. The analog-to-digital converter of claim 1, wherein thedigital-to-analog converter is a capacitive digital-to-analog convertercomprising: a plurality of capacitors; and a plurality of switchescoupled to each of the capacitors; and wherein the successiveapproximation circuitry is configured to set the switches according tobits of the multi-bit digital threshold value while operating in thecomparison mode.
 3. The analog-to-digital converter of claim 2, whereinthe successive approximation circuitry is configured to apply the outputsignal generated by the comparator to determine whether each of theswitches is to be opened or closed while operating in the conversionmode.
 4. The analog-to-digital converter of claim 1, wherein thesuccessive approximation circuitry is configured to disregard the outputsignal generated by the comparator while operating in the comparisonmode.
 5. The analog-to-digital converter of claim 1, wherein thesuccessive approximation circuitry is configured to disregard themulti-bit digital threshold value while operating in the conversionmode.
 6. The analog-to-digital converter of claim 1, wherein thesuccessive approximation circuitry is configured to execute a binarysearch for a digital value corresponding to a voltage of an analog inputsignal while operating in the conversion mode.
 7. A measurement system,comprising: an analog multiplexer; and a successive approximationregister analog-to-digital converter coupled to an output of the analogmultiplexer, the successive approximation register analog-to-digitalconverter configured to operate in a comparison mode and a conversionmode; wherein: in the comparison mode, the successive approximationregister analog-to-digital converter is configured to: convert amulti-bit digital threshold value received from circuitry external tothe successive approximation register analog-to-digital converter to ananalog threshold signal; and compare a signal received from the analogmultiplexer to the analog threshold signal.